1. Field of the Invention
The present invention relates to a digital PB exchanger with a Multi-processor control system, and more particularly to a Digital PB exchanger using an Asynchronous transfer mode (hereinafter, referred to as an ATM) for data transferring between processors.
2. Description of the Related Art
FIG. 1 is a general block diagram showing a connection between processors in a conventional Digital PB exchanger with the Multi-processor control system. A conventional Digital PB exchanger with a Multi-processor control system consists of a plurality of Processor units 71 to 76 for load sharing and function sharing. The Digital PB exchanger comprises bus 7, used exclusively for data Communication between processors, as means for performing data transmitting between processors and Bus interface circuits 81 to 86 between processors which provide an interface between the bus used exclusively for data Communication between processors and Processor units 71 to 76. In addition, buses which are used exclusively for connections between Time division switches 91 to 94 and Space division switch 6 are arranged. Thus, the Digital PB exchanger with a Multi-processor control system is realized by these components.
FIG. 2 is a block diagram showing a conventional Connection system between processors, which is disclosed in Japanese Patent Application Laid Open Tokkaihei 2-277340. The conventional Connection system between processors shown in FIG. 2 is constituted by connecting a plurality of Processors 100 to 10n to ATM switch 200. Each of Processors 100 to 10n includes an ATM interface circuit, and is connected to ATM switch 200 via the ATM switch interface circuit. Thus, the Connection system between processors shown in FIG. 2 realizes data communication between processors.
The first problem involved in the prior art is that the conventional Digital PB exchanger with the Multi-processor control system requires the bus for data communication and the buses for Time division switches 91 to 94, separately. The connections between the processors and ATM switch 220 are disclosed in the Japanese Patent Application Laid Open Tokkaihei 2-277340. The bus for data communications between processors has been merely disclosed in the prior art. However, the bus such as for the Time division switch, which is different from the bus for data communications between processors, has not been disclosed yet.
The reason for this is that the signal form and the transmitting speed are different between the bus for the data communication between processors and the bus for the connections for the Time division switches so that the Digital PB exchanger with the Multi-processor control system can not be realized by simply multiplexing.
The second problem involved in the prior art is as follows. The distance between the bus used for data communication between processors and the bus used for the connections for the Time division switches can not be set to be longer so that the buses must be installed in a single system and it is impossible to use them extending over more than two systems. The reason of the presence of the second problem is that the communication speed of both of the aforementioned buses is high and communication trouble such as bit error might be caused unfortunately in case of long distance between the buses.